The present invention relates to the manufacturing of semiconductor devices, and more particularly, to copper and copper alloy metallization in semiconductor devices.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the su-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as xe2x80x9cdamascenexe2x80x9d-type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or interlayer dielectric (ILD) between vertically spaced metallization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as inter-metal dielectric layers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization levels.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization level and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metallization level usually results in high contact resistance.
Another attempted solution for the W plug interconnect problem involves depositing W using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization levels. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
One drawback of using copper or Cu-based alloys is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as silicon oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride, titanium nitride, or tungsten nitride are used as barrier materials for copper. A thin adhesion layer formed of an adhesion material, such as tantalum, titanium, or tungsten is typically first deposited on the dielectrics or via to ensure good adhesion and good electrical contact of the subsequently deposited barrier layers to underlying doped regions and/or conductive regions. Adhesion/barrier layer stacks formed of adhesion/barrier materials such Ta/TaN, Ti/TiN, and W/WN have been found to be useful as adhesion/barrier material combination for copper interconnects.
However, even with these various types of barrier layers, copper is still subject to strong electromigration, or the movement of copper atoms along the channels or vias under the influence of electrical current. Electromigration also tends to occur at the copper/barrier interface. One proposed solution to the electromigration problem has been to dope the copper with various dopants. These dopants typically have two effects. First, the dopants act to slow the lattice and grain boundary diffusion of copper atoms. Second, depending on the dopant and the concentration of the dopant, the dopant can slow the migration of copper atoms along the copper/barrier interface or a copper/passivation interface. After doping, the entire semiconductor device is subject to a thermal annealing to activate the dopants.
One problem associated with doping copper is that activation of the dopants by thermal annealing requires that all the features on a semiconductor device be subject to annealing and not just the features that are to be annealed. As is well known in the art, many of the features on a semiconductor device are sensitive to heat, and these features can be detrimentally affected by a thermal annealing process. As such, the parameters of current thermal annealing processes must be chosen so as to not detrimentally affect other features on the semiconductor. Another problem associated with thermal, annealing is that the process is relatively time-consuming because a considerable length of time is required to heat the semiconductor device to the proper annealing temperature.
Another problem associated with the above-identified processes is that the dopant only penetrates the top of the copper layer. As such, the dopant may not completely reach all regions in which the presence of dopants can reduce electromigration. Accordingly, a need exists for an improved method of forming copper plugs and copper metallization that allows for improved dopant concentration within the plugs or metallization and while providing a less time-consuming process and greater process flexibility.
This and other needs are met by embodiments of the present invention which provide a semiconductor device. The semiconductor device includes a first metallization level, a first etch stop layer, a dielectric layer, and an opening. The first etch stop layer is disposed over the first metallization level and the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer. The first metallization level includes a first metal feature, and metal within the opening forms a second metal feature. Dopants that reduce electromigration are introduced into the metal, and the dopants are activated by laser thermal annealing. The metal can be copper or a copper alloy.
By activating the dopants with laser thermal annealing, the total energy being supplied to the semiconductor device by the laser thermal annealing process can be reduced. Furthermore, the laser thermal annealing process is considerably shorter than a typical furnace annealing process. Also, the laser thermal annealing process more evenly distributes the dopants within the metal.
In another aspect of the invention, a concentration of the dopants within the metal in a lower portion of the second metal feature proximate the first metal feature is greater than a concentration of dopants in a central portion of the second metal feature. Also, a concentration of the dopants within the metal in an upper portion of the second metal feature is greater than a concentration of dopants in the central portion of the second metal feature. The upper and lower portions have depths equal to about 5% to about 15% of a depth of the second feature, and the central portion has a depth equal to about 70% to about 90% of a depth of the second feature.
In a further embodiment of the present invention, a method of manufacturing a semiconductor device is also disclosed. The method of manufacturing includes forming a first etch stop layer over the first metallization level; forming a dielectric layer over the first etch stop layer; forming an opening through the dielectric layer and the first etch stop layer; and filling the opening with metal to form a second metal feature. Dopants are then introduced into the metal and the metal is laser thermal annealed to activate the dopants.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.